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Ultraperformance Nanophotonic Intrachip Communications (UNIC)
Program Manager: Dr. Jagdeep Shah
UNÍC focuses on demonstrating high-performance, CMOS-compatible photonic technology for high-throughput, non-blocking and power-efficient intrachip photonic communications networks. UNÍC addresses the challenge of demonstrating high performance photonic devices with significantly smaller area and significantly lower power consumption compared to the current state-of-the-art for such devices fabricated in CMOS-compatible processes. UNÍC will demonstrate technology that will enable scalable, high-bandwidth intrachip and off-chip communications for advanced multi-core microprocessor chips in a future technology node. The program will experimentally demonstrate device and chip-scale photonic link performance that will validate the architecture, perform a detailed analysis of system and application performance benefits, and experimentally demonstrate links between communications between advanced microprocessors through intrachip photonic links.
Trends in transistor scaling suggest that the raw computational power realizable on a single microprocessor chip will continue to grow in the future. However, it is highly unlikely that intrachip electrical communications can provide the bandwidth required to maintain system balance (1 Byte/s of communication bandwidth for 1 operation/s of computation power) for future microprocessors within the available power budget. Increasing system imbalance will lead to decreasing computational efficiency (the ratio of actual to raw computational power). UNÍC addresses this challenge by developing photonic communication technologies integrated at the chip-scale to provide the required bandwidth and maintain system balance for future microprocessors within the tight power constraints. Such a capability would dramatically impact the actual runtime performance of DoD-relevant computing tasks such as power-starved embedded applications, and supercomputing.
The UNÍC program requires research to develop innovative approaches that enable revolutionary advances in science, devices, and/or systems in the following areas:
(I) Photonic Network Architecture:
The first major area of interest is development of flexible, non-blocking and scalable architectures for the intrachip photonic communication networks for an advanced multi-core microprocessor in a future technology node. Non-blocking networks with low latency, narrow latency distributions, large communication bandwidths (to accommodate all expected traffic) and other characteristics that minimize programming effort are of particular interest. Analysis of system performance benefits for the networks is an integral part of this effort.
(II) Photonic Devices:
The second major area of interest is aggressive development of photonic devices required for such intrachip photonic networks. The technical requirements associated with producing a chip-scale photonic interconnect network capable of providing the necessary bandwidth and power efficiency are extremely demanding. Accordingly, the photonic devices must reduce device areas and power dissipation significantly compared to state-of-the-art while at the same time enhancing performance on modulation speed, detectivity, waveguide loss and other characteristics. Various photonic devices such as modulators, detectors, vertical/interlayer couplers, wavelength mux/demux, wavelength filters, waveguides, and optical amplifiers may be required. Devices must be compatible with standard CMOS processing so that electronics for modulator drivers, detector amplifiers etc. can be integrated with photonics.
(III) Integration/Demonstrations:
The third major area of interest is to integrate large numbers and high densities of photonic devices on a chip and validate the network architecture/design through appropriate demonstrations. In addition to developing robust, high-yield fabrication processes, complete photonic links, along with associated electronic control/support circuitry must be fabricated and tested to demonstrate the ability to transfer data optically at the chip-scale with a target energy-per-bit. The culmination of this effort is a chip-scale, high-performance photonic link demonstration that experimentally validates the intrachip photonic communication network design, and an aggressive demonstration of advanced microprocessors communicating through a chip-scale photonic link.