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Three Dimensional Integrated Circuits (3D IC)
Program Manager: Dr. Michael Fritze
3-D integrated circuits offer significant performance benefits over two dimensional (2-D) integrated circuits based on the electrical and mechanical properties arising from the new geometrical arrangement. In 2-D integrated circuits, the reduction of transistor features over time ("Moore's Law") provides ever greater densities of transistors and faster clock rates, but is now leading to circuits where the spatial domain of signal propagation between clock edges is smaller than the total chip area. Decreases in this span of signal synchronicity is leading to a paradigm shift in micro-architectures, from designs optimized for serial computational algorithms (Von Neumann) toward communication-driven designs of chip-scale micro-area networks of processing elements. Access to the third dimension will significantly simplify chip-scale communications and the transfer of information among the processing elements and also provide rapid access to memory and configurable logic. For example, 3-D technology would enable extremely dense solid-state memory to be arrayed within a few microns of the processing elements, greatly reducing access times. The 3-D arrangement also provides opportunities for new circuit architectures based on the geometrical ability to have greater numbers of interconnections among multi-layer active circuits. For example, a typical 2-D field programmable gate array (FPGA) requires on-chip interconnections that grow faster than linearly with gate count. These reconfigurable circuits are limited in performance by the complexities of their internal interconnections. A 3-D FPGA would overcome the interconnect limitations, resulting in greater silicon efficiency per function (number of used gates/total number of gates), faster signal/data throughput, and faster switching of the gate-level configuration.
The active devices (transistors, diodes, thyristors, etc.) of conventional highly integrated circuits are essentially two dimensional (2-D), being confined to a plane in the upper surface of a semiconductor crystal with several layers of fixed interconnects separated by dielectrics above. As planar device miniaturization continues to its ultimate limits, the complexity of circuit interconnections for 2-D devices becomes a limitation for performance and drives up power dissipation. 3-D integrated circuits consist of active devices that are not confined to a single planar layer and are intimately commingled with interconnections can solve these limitations and enable new circuit architectures. True 3-D integrated circuits can operate at higher clock rates and can consume less power over their 2-D implementations since the 3-D arrangement minimizes the length of lossy circuit interconnects.
Advances in integration technologies such as layer bonding, direct growth of materials, and micro-assembly have demonstrated the mechanical technical capability to produce multiple layers (or large regions) of single crystal semiconductors with insulated barriers in between the layers. These processes, or other like methods, can now be further developed and exploited to build true 3-dimensional (3-D) integrated circuits with multiple layers of active devices and interconnections. This new 3-D Integrated Circuits initiative is intended to greatly advance 3-D design and process technologies for new types of circuit architectures as well as for general types of integrated circuits for military applications. These 3-D integrated circuits are likely to consist of a heterogeneous mixture of circuit functions including high throughput processing elements; dense, high speed memories; dedicated functions; reconfigurable logic; etc.
Among the goals of this initiative is the development of a robust 3-D integrated circuit technology for producing high performance circuits, through the development of advanced fabrication capabilities and the design tools needed to fully and efficiently exploit the technology. The objectives of this initiative include the identification of military-relevant applications where 3-D integration technologies provide clear advantages and to develop the most promising technologies to establish the benefits enabled by integrated circuit interconnected in a 3-D fashion, with the right scale and density and size in true 3-D integrated circuits. A critical objective of the program is to compare circuits designed and fabricated in 3-D technology to 2-D implementations, and demonstrate linear increases in performance (as measured by circuit throughput/power dissipation/chip footprint) with respect to the number of layers.
**Updated content forthcoming, pending public release approval.**