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Clockless Logic (CLASS)
Program Manager: Dr. Dean Collins
Overview
The Clockless Logic, Analysis, Synthesis and Systems (CLASS) program will enable the continued advances of complex electronic systems by eliminating the requirement for a system clock and thereby reducing the development costs of high performance integrated circuits closer to that of general processors. In addition to drastically reduced design effort, Clockless Logic can also have the advantage of operating over a wide range of power and speed, improved energy utilization, reduced EMI and tolerance to voltage and process variation. The CLASS program seeks to demonstrate the significant advantages of asynchronous logic implementations for large, complex circuits and develop a design environment that will encompass the entire process from system description through circuit verification, including EDA/CAD tools required for logic design, optimization and test of asynchronous circuits. The advantages will be proven by an exact comparison with a large, synchronous chip performing in a system of military importance.
The key technical challenge of the CLASS program will be the implementation of methodologies and a supported IC design tool environment for the analysis, synthesis, and verification of complex asynchronous circuit blocks. Specification of a total tool flow for both control and data path design will result. A complex (approximately 50M transistor) asynchronous SoC, with a goal of at least 10X reduction in design time and cost compared to that projected for an equivalent synchronous design, will be fabricated and tested. Areas of significant performance advantage such as speed, power, EMI etc. that can be attributed to the asynchronous design will be identified and quantified. A generic asynchronous integrated circuit design methodology, appropriate to numerous applications requiring a significant reduction in design resources, design complexity, power requirements, and EMI emissions, is the goal. This design environment is expected to enable SoCs of a complexity not practical with the existing synchronous methods.
**Updated content forthcoming, pending public release approval.**