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Compound Semiconductor Materials On Silicon (COSMOS)
Program Manager: Dr. Mark Rosker
The development of CS electronics has been motivated by their unique materials properties relative to those of silicon. However, the advantages of the incumbency of Si integrated circuits (ICs), the enormous investment that has been made in such technologies, the remarkable progress in VLSI integration and device scaling, and the dramatic cost reductions for Si ICs have combined to limit the market penetration of CS technologies. Given these trends, it has been increasingly clear that the future of CS electronics depends not on supplanting silicon, but rather on heterogeneous integration of CS with silicon.
The objective of the COmpound Semiconductor Materials on Silicon (COSMOS) program is to develop a viable process for the fine-scale heterogeneous integration of CS devices with standard Si CMOS and to establish that this integration enables superior performance in specific mixed-signal circuit demonstrators. The program will focus on four major technical areas of interest: placement of CS devices, heterogeneous integration, dense heterogeneous interconnects, and yield enhancement. COSMOS will culminate in the demonstration of a heterogeneously-integrated 16-bit analog-to-digital converter (ADC). This will be accomplished by placing CS and Si-based transistors in ≤ 5μm minimum proximity, with ≤ 5μm minimum pitch of the heterogeneous interconnect vias and yield of ≥ 99.99% of the heterogeneous interconnects.
The COSMOS program will be conducted in three phases. Phase I will develop and demonstrate a viable process technology to integrate CS and Si CMOS transistors on a very short size-scale within a small circuit (transistor-scale integration technology). The specific circuit demonstrator to validate performance will be a standard differential amplifier, consisting of five transistors. Phase II will focus on yield enhancement & circuit integration. The objectives of this phase are to significantly improve both the yield and the density of the heterogeneous interconnect process, the latter achieved through a significant reduction in the pitch of the heterogeneous interconnects. The overall goal of this phase will be to demonstrate a heterogeneously-integrated 13-bit digital-to-analog converter (DAC) achieving 78 dBc of SFDR at 1GHz output frequency. In Phase III the COSMOS process will be scaled to a much larger circuit, conclusively demonstrating that fine-scale heterogeneous integration can be realized on a large scale. This Phase will result in a heterogeneously-integrated 16-bit analog-to-digital converter (ADC) which will support 98 dBc of SFDR across a 500-MHz bandwidth.