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Self-HEALing mixed-signal Integrated Circuits (HEALICs)
Program Manager: Dr. Sanjay Raman
Advances in integrated circuit technologies have enabled the single-chip integration of multiple analog/RF and digital functions, resulting in complex mixed-signal Systems-on-a-Chip (SoCs) well suited for meeting the stringent and unique requirements of Department of Defense (DoD) electronic microsystems. Such high performance SoC designs have been made feasible by the increased speed and higher density available in modern nanometer-scale IC processes. A major consequence, however, of the drive towards ever smaller transistor gate lengths is an exponential increase in intra-wafer and intra-die process variations that have a direct impact on circuit performance. Often, designers must relax performance goals to guarantee a sufficient post-fabrication performance yield.
The core goal of the HEALICs program is to regain this lost performance by adding sensing and control circuitry that will compensate for the process variations in situ., which will ultimately allow designers to focus on the performance goals and not on yield related issues. This initiative is not limited to any particular type of circuit or control approach. Rather, it aims to develop techniques and technologies that allow any mixed-signal design to be runtime corrected at the SoC level. The technologies developed under this program will also address environmental variations and ageing, significantly enhancing the long-term reliability of DoD electronic systems.
HEALICs efforts start with a complex, mixed-signal baseline SoC design that had been either determined to not be practical due to processing technology variability or realized with extremely poor (near zero) performance yield as measured by target performance metrics. Performers will demonstrate that the performance yield of the baseline SoC can be dramatically increased by the introduction of on-chip self-healing circuits.
In Phase I, performers will design and fabricate key sub-blocks of a target mixed-signal core with local self-healing control added. Further, the performers will develop robust, global self-healing control algorithms for integration with the sub-blocks into a complex mixed-signal design. Phase I goals are a performance yield >75% upon activation of self-healing and power consumption overhead <10%.
In Phase II, performers will integrate the previously demonstrated self-healing mixed-signal core into a larger SoC. Phase II goals are a performance yield >95% upon activation of self-healing, and power consumption overhead <5%.
An ongoing activity of this program will be the development of self-healing mixed-signal IP core libraries for next-generation DoD electronic microsystems.