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Photonic Analog Signal Processing Engine with Reconfigurability (PHASER)
Program Manager: Dr. Michael Haney
The objective of the PhASER program is to develop a fundamental photonic integrated circuit (PIC), termed "Unit Cell", which can act as a reconfigurable building block in the formation of a high-throughput, low-power, analog signal processor. The intent of this program is to enable scalable PIC-based analog signal processors that are flexible and scalable enough to synthesis microwave signal filters whose characteristics are specific to a variety of applications and which may also be reconfigured at real-time rates for anticipated applications that require adaptive filter characteristics.
PhASER technology will be an enabler for anticipated future applications that have ultrahigh throughput sensor signal processing requirements, but are highly constrained in size weight and power. Of particular interest are high-bandwidth problems for which electronic analog-to-digital converters cannot achieve the desired dynamic range, and where performing the needed computations in the analog domain may prove advantageous. DARPA envisions the PhASER program will enable signal processing with greater than Tera-operations per second (TOPS) per Watt (W) of effective computing throughput and thus overcoming the limits of conventional silicon-based digital signal processing technology.