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Radiation Hardening by Design (RHBD)

The objective of the Radhard by Design Program is to develop and demonstrate design and layout techniques to support the fabrication of strategically radiation hardened integrated circuits from pure design approaches; no changes in fabrication or materials. The program is focused on foundry-type silicon technologies, ultra-deep submicron (e.g. < = 130 nm technology) geometries, and digital / analog / mixed signal integrated circuits. Specific interest is in the demonstration of design techniques for producing radiation hardened devices on standard commercial foundry flows, without any modification of the existing process or violation of design and layout rules, with corresponding electrical performance and area penalties of less than or equal to one generation.

The first phase of this program is primarily concerned with demonstrating the efficacy of Rad Hard by design (RHBD) from a technology stand point. Towards this end, both digital and analog devices and simple circuits will be designed, fabricated and tested. Target foundry technologies as appropriate are 130 nm bulk silicon and 130 nm SiGe BiCMOS. This program has been partnering with the DoD Trusted Foundry Program for access to leading-edge semiconductor technologies and design libraries and designed circuit cores. Radiation performance criteria for the test structures of this phase are as follows:

Table 1: Radiation Performance Critera
		Requirement	Goal
Total Dose		1 Mrad	2Mrad
Dose Rate	Latch up	5e10 rad(Si)/sec	1e12 rad(Si)/sec
		1e9 rad(Si)/sec	1e10 rad(Si)/sec
SEE	Latch up	None
	Upset	LET > 15	LET>20
		< 1e-10 errors/bitday

Additionally, these radiation performance target values should be achieved with less than a one technology generation penalty in size, speed or power.

The next phase will refine the RHBD techniques and develop more accurate device models from the data generated in phase one and design and fabricate both test structures and complex devices. Digital libraries will be developed to support synthesis of an ARM 10 processor core or equivalent complexity core. Also a large static random access memory (SRAM) array may be fabricated. Mixed signal device complex structures will include an A/D converter and other analog building blocks such as phase locked loops, op amps, I/Q converters etc. More complex integrated circuits may be fabricated based on technology performance and characteristics. Radiation and performance specifications remain the same as phase one.

**Updated content forthcoming, pending public release approval.**